This disclosure relates generally to semiconductor devices, and more specifically to semiconductor memory devices. The memory device may hold a number of physical signals (e.g., a charge, voltage, polarization, etc.) each corresponding to a logical value. There may be a small difference between the physical signal representing a ‘high’ logical value and the physical signal representing a ‘low’ logical value. It may be desirable to amplify the physical signals of the memory cells into logical signals (e.g., voltages) which can be more easily used by other components of the semiconductor device and may have a more easily distinguishable difference between ‘high’ and ‘low’ logical states.
The memory device may include a memory cell array including a number of word lines (rows) and bit lines (digit lines, columns). Memory cells each containing data (e.g., a bit of data) are disposed at each intersection of word lines and bit lines. The data may be stored in each memory cell as a physical signal which, when accessed results in an electrical signal representing one or more logical values. The logical values may be binary values used in computing systems (e.g., ‘1’ and ‘0’, ‘true’ and ‘false’, ‘high’ and ‘low’, etc.).
Sense amplifiers may be coupled to the memory cells (e.g., coupled to bit lines to which accessed memory cells are coupled) to convert and/or amplify the signals of selected memory cells during a read operation. For example, the sense amplifier may sense the signal from the memory cell and may also increase the voltage difference a ‘high’ logical value and a low ‘logical’ value. The sense amplifier may be a high power component of the memory and/or may have difficulty sensing small differences between the signals representing the different logical values. It may be desirable to reduce the complexity and/or power requirements of the sense amplifiers.